In this paper, a method is introduced how to process the Discrete Fourier Transform (DFT) by a singlelayer neural network with a linear transfer function. By implementing the sugg...
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
Srinivas Chellappa, Franz Franchetti, Markus P&uum...
We propose a high-level language based on rst order logic for expressing synchronization in concurrent object-oriented programs. The language allows the programmer to declaratively...
In this paper, an efficient VLSI architecture for a fast computation of the 2-D discrete wavelet transform (DWT) is proposed. The architecture employing a three-stage cascade in p...
Abstract Barrier synchronizations can be very expensive on multiprogramming environment because no process can go past a barrier until all the processes have arrived. If a process ...