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» Synchronization of periodic clocks
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FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 8 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 8 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
HOST
2009
IEEE
14 years 6 months ago
Detecting Trojan Circuit Attacks
Abstract—Rapid advances in integrated circuit (IC) development predicted by Moore’s Law lead to increasingly complex, hard to verify IC designs. Design insiders or adversaries ...
Gedare Bloom, Bhagirath Narahari, Rahul Simha
ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
14 years 5 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou
DELTA
2008
IEEE
14 years 5 months ago
Improved Policies for Drowsy Caches in Embedded Processors
In the design of embedded systems, especially batterypowered systems, it is important to reduce energy consumption. Cache are now used not only in general-purpose processors but a...
Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroak...