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ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
13 years 7 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
PPOPP
2003
ACM
14 years 25 days ago
Improving server software support for simultaneous multithreaded processors
Simultaneous multithreading (SMT) represents a fundamental shift in processor capability. SMT's ability to execute multiple threads simultaneously within a single CPU offers ...
Luke McDowell, Susan J. Eggers, Steven D. Gribble
IPPS
2009
IEEE
14 years 2 months ago
Enabling high-performance memory migration for multithreaded applications on LINUX
As the number of cores per machine increases, memory architectures are being redesigned to avoid bus contention and sustain higher throughput needs. The emergence of Non-Uniform M...
Brice Goglin, Nathalie Furmento
ECOOP
2010
Springer
14 years 12 days ago
Self-Replicating Objects for Multicore Platforms
The paper introduces Self-Replicating Objects (SROs), a new nt programming abstraction. An SRO is implemented and used much like an ordinary .NET object and can expose arbitrary us...
Krzysztof Ostrowski, Chuck Sakoda, Ken Birman
SC
1992
ACM
13 years 11 months ago
Willow: A Scalable Shared Memory Multiprocessor
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
John K. Bennett, Sandhya Dwarkadas, Jay A. Greenwo...