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SBCCI
2009
ACM
188views VLSI» more  SBCCI 2009»
14 years 4 months ago
Low-power inter-core communication through cache partitioning in embedded multiprocessors
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
Chenjie Yu, Xiangrong Zhou, Peter Petrov
SIES
2008
IEEE
14 years 4 months ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl
IPCCC
2007
IEEE
14 years 4 months ago
Optimal Cluster Head Selection in the LEACH Architecture
LEACH (Low Energy Adaptive Clustering Hierarchy) [1] is one of the popular cluster-based structures, which has been widely proposed in wireless sensor networks. LEACH uses a TDMA ...
Haiming Yang, Biplab Sikdar
IPPS
2007
IEEE
14 years 4 months ago
A Portable Framework for High-Speed Parallel Producer/Consumers on Real CMP, SMT and SMP Architectures
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
Richard T. Saunders, Clinton L. Jeffery, Derek T. ...
NCA
2007
IEEE
14 years 4 months ago
Improving Network Processing Concurrency using TCPServers
Exponentially growing bandwidth requirements and slowing gains in processor speeds have led to the popularity of multiprocessor architectures. Network stack parallelism is increas...
Aniruddha Bohra, Liviu Iftode