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DAC
1995
ACM
14 years 23 hour ago
Hierarchical Optimization of Asynchronous Circuits
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
Bill Lin, Gjalt G. de Jong, Tilman Kolks
FORMATS
2009
Springer
14 years 3 months ago
Synthesis of Non-Interferent Timed Systems
In this paper, we focus on the synthesis of secure timed systems which are given by timed automata. The security property that the system must satisfy is a non-interference propert...
Gilles Benattar, Franck Cassez, Didier Lime, Olivi...
EURODAC
1995
IEEE
127views VHDL» more  EURODAC 1995»
14 years 20 hour ago
Layout synthesis for datapath designs
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charle...
LREC
2010
176views Education» more  LREC 2010»
13 years 10 months ago
Vergina: A Modern Greek Speech Database for Speech Synthesis
The present paper outlines the Vergina speech database, which was developed in support of research and development of corpus-based unit selection and statistical parametric speech...
Alexandros Lazaridis, Theodoros Kostoulas, Todor G...
ICASSP
2010
IEEE
13 years 8 months ago
HMM-based pseudo-clean speech synthesis for splice algorithm
In this paper, we present a novel approach to relax the constraint of stereo-data which is needed in a series of algorithms for noise-robust speech recognition. As a demonstration...
Jun Du, Yu Hu, Li-Rong Dai, Ren-Hua Wang