115 search results - page 11 / 23 » Synthesis of Asynchronous Hardware from Petri Nets |
ASYNC
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
20
Voted
ENTCS
2010
13 years 7 months ago
2010
This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context o...
ACSD
2003
IEEE
14 years 24 days ago
2003
IEEE
This paper presents a synthesis approach for reactive systems that aims at minimizing the overhead introduced by the operating system and the interaction among the concurrent task...
ISTA
2008
13 years 9 months ago
2008
This contribution suggests a novel approach for a systematic generation of a process model in an informal environment. It is based on the claim that the knowledge about the process...
CAV
2005
Springer
14 years 1 months ago
2005
Springer
In this paper, we present the features of Romeo, a Time Petri Net (TPN) analyzer. The tool Romeo allows state space computation of TPN and on-the-fly model-checking of reachabilit...