High Level Synthesis of Timed Asynchronous Circuits

This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthesis is used to allow for global and timing optimization. In order to reduce the overhead in resetting phases, a protocol called early acknowledgment protocol and its STG generation technique are proposed. In this protocol, the state variables inserted to guarantee that STGs have CSC usually cause no overhead. The experiments to synthesize a portion of a DCT circuit show that the proposed method can handle a nontrivial example and produce a smaller and faster circuit than a previous approach. Key Words: High level synthesis, SpecC, resource allocation/scheduling, logic synthesis, timed STGs, Balsa

• Type: Conference
• Year: 2005
• Where: ASYNC
• Authors: Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers
• Keywords: ASYNC 2005, Hardware, Logic Synthesis, Logic Synthesis Approach, State-based Logic Synthesis