Formal specifications play an increasingly important role in system design-flows. Yet, they are not always easy to deal with. In this paper we present RATSY, a successor of the R...
Roderick Bloem, Alessandro Cimatti, Karin Greimel,...
In this paper, two anticontrol algorithms for synthesis of discrete chaos are introduced. In these algorithms, the control parameter of a discrete dynamical system is switched, ei...
In this paper, the problem of synthesizing controllers that ensures non interference for multilevel security dense timed discrete event systems modeled by an extension of Timed Au...
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
We present novel techniques for efficient controller synthesis for untimed and timed systems with respect to invariance and reachability properties. In the untimed case, we give al...