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    » Synthesis of networks on chips for 3D systems on chips
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    FAC
    2008
    97views more  FAC 2008»
    A functional formalization of on chip communications
    13 years 8 months ago
    A functional formalization of on chip communications
    Download  www.cs.ru.nl
    This paper presents a formal model and a systematic approach to the validation of communication tures at a high level of abstraction. This model is described mathematically by a fu...
    Julien Schmaltz, Dominique Borrione
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    IJCNN
    2000
    IEEE
    133views Neural Networks» more  IJCNN 2000»
    A 2D Neuromorphic VLSI Architecture for Modeling Selective Attention
    14 years 1 months ago
    A 2D Neuromorphic VLSI Architecture for Modeling Selective Attention
    Download  www.ini.uzh.ch
    Selectiveattentionis a mechanismsused to sequentiallyselectthe spatiallocationsof salientregionsin the sensor’sfieldof view. This mechanism overcomesthe problem of flooding limi...
    Giacomo Indiveri
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    PPL
    2008
    185views more  PPL 2008»
    On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
    13 years 8 months ago
    On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
    Download  gram.eng.uci.edu
    As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
    Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
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    IPPS
    2007
    IEEE
    192views Distributed And Parallel Com...» more  IPPS 2007»
    Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
    14 years 3 months ago
    Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
    Download  www.cecs.uci.edu
    The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
    Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
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    GECCO
    2007
    Springer
    268views Optimization» more  GECCO 2007»
    Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm
    14 years 2 months ago
    Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm
    Download  www.cs.bham.ac.uk
    This work presents a novel approach to filter synthesis on a field programmable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPA...
    Joachim Becker, Stanis Trendelenburg, Fabian Henri...
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