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» Synthesis of networks on chips for 3D systems on chips
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ISQED
2003
IEEE
109views Hardware» more  ISQED 2003»
14 years 1 months ago
Modeling and Analysis of Power Distribution Networks for Gigabit Applications
—As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) acc...
Wendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim...
DAC
2011
ACM
12 years 8 months ago
Supervised design space exploration by compositional approximation of Pareto sets
Technology scaling allows the integration of billions of transistors on the same die but CAD tools struggle in keeping up with the increasing design complexity. Design productivit...
Hung-Yi Liu, Ilias Diakonikolas, Michele Petracca,...
JCP
2008
119views more  JCP 2008»
13 years 8 months ago
Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent con...
Omar S. Elkeelany, Adegoke Olabisi
NOCS
2007
IEEE
14 years 2 months ago
Transaction-Based Communication-Centric Debug
Abstract— The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC...
Kees Goossens, Bart Vermeulen, Remco van Steeden, ...
CASES
2009
ACM
14 years 3 months ago
Towards scalable reliability frameworks for error prone CMPs
As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at vario...
Joseph Sloan, Rakesh Kumar