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» Synthesis of networks on chips for 3D systems on chips
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ICDM
2006
IEEE
147views Data Mining» more  ICDM 2006»
14 years 2 months ago
Adaptive Parallel Graph Mining for CMP Architectures
Mining graph data is an increasingly popular challenge, which has practical applications in many areas, including molecular substructure discovery, web link analysis, fraud detect...
Gregory Buehrer, Srinivasan Parthasarathy, Yen-Kua...
SLIP
2003
ACM
14 years 1 months ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
ISLPED
2010
ACM
153views Hardware» more  ISLPED 2010»
13 years 8 months ago
Leakage minimization using self sensing and thermal management
We have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for...
Alireza Vahdatpour, Miodrag Potkonjak
GLOBECOM
2008
IEEE
13 years 8 months ago
Highly Memory-Efficient LogLog Hash for Deep Packet Inspection
As the network line rates reach 40 Gbps today and 100 Gbps in the near future, performing deep packet inspection (DPI) in the Network Intrusion Detection and Prevention Systems (NI...
Masanori Bando, N. Sertac Artan, H. Jonathan Chao
TVLSI
1998
88views more  TVLSI 1998»
13 years 8 months ago
Time multiplexed color image processing based on a CNN with cell-state outputs
—A practical system approach for time-multiplexing cellular neural network (CNN) implementations suitable for processing large and complex images using small CNN arrays is presen...
Lei Wang, José Pineda de Gyvez, Edgar S&aac...