10159 search results - page 104 / 2032 » System Design Validation Using Formal Models |
ICEISSAM
2004
13 years 9 months ago
2004
Due to the different nature of the available dynamic interactions between components afforded by some middleware infrastructure, distributed information systems (DIS) behave differ...
ICCD
2000
IEEE
13 years 11 months ago
2000
IEEE
A major obstacle to widespread acceptance of formal verification is the difficulty in using the tools effectively. Although learning the basic syntax and operation of a formal ver...
FLAIRS
2004
13 years 9 months ago
2004
TURING Test technologies are promising ways to validate AI systems which may have no alternative way to indicate validity. Human experts (validators) are often too expensive to in...
FDL
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract. The paper proposes a simulation-based method for validating analog and mixed-signal circuits, using the hybrid systems methodology. This method builds upon RRT (Rapidly-e...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
—SystemC is a system-level modeling language that offers a wide range of features to describe concurrent systems rent levels of abstraction. The SystemC standard permits simulato...