10159 search results - page 21 / 2032 » System Design Validation Using Formal Models |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
ACSC
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes our experience when applying formal methods in the design of the tourist information system TIP, which presents context-sensitive information to mobile users ...
CONCUR
2000
Springer
14 years 7 days ago
2000
Springer
Concurrency is an essential element of abstract models for embedded systems. Correctness and e ciency of the design depend critically on the way concurrency is formalized and imple...
UML
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
CCE
2011
13 years 2 months ago
2011
Selective liquid membranes have been traditionally employed for liquid/liquid and gas/liquid mass transfer in a wide range of applications. In particular, the Emulsion Pertraction...