10159 search results - page 39 / 2032 » System Design Validation Using Formal Models |
ICECCS
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract—Plugin-based application design has become increasingly popular in recent years, and has contributed to the success of a range of very different applications including ...
EWSA
2004
Springer
14 years 1 months ago
2004
Springer
This paper provides an overview on the approach of the IST OMEGA project for the development of correct software for embedded systems based on the use of UML as modelling language....
DSD
2004
IEEE
13 years 11 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
FATES
2004
Springer
14 years 1 months ago
2004
Springer
A Time Action Lock is a state of a Real-time system at which neither time can progress nor an action can occur. Time Action Locks are often seen as signs of errors in the model or ...
ASM
2010
ASM
14 years 5 months ago
2010
ASM
Abstract. The aim of this paper is to gradually introduce formalism in the requirement engineering phase in order to facilitate its validation. We analyze and elicit our requiremen...