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» System Design Validation Using Formal Models
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DSD
2005
IEEE
116views Hardware» more  DSD 2005»
14 years 1 months ago
Validation of Embedded Systems Using Formal Method Aided Simulation
This paper proposes a validation approach, based on simulation, which addresses problems related to both state space explosion of formal methods and low coverage of informal metho...
Daniel Karlsson, Petru Eles, Zebo Peng
ECMDAFA
2007
Springer
100views Hardware» more  ECMDAFA 2007»
14 years 2 months ago
Reverse Engineering Models from Traces to Validate Distributed Systems - An Industrial Case Study
The paper targets the applicability of model-driven methodologies to the validation of complex systems and presents a case study of a mobile radio network. Validation relies on the...
Andreas Ulrich, Alexandre Petrenko
DAC
1997
ACM
14 years 1 days ago
Toward Formalizing a Validation Methodology Using Simulation Coverage
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
Aarti Gupta, Sharad Malik, Pranav Ashar
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 11 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
HASE
1998
IEEE
14 years 3 days ago
Formal Specification in Collaborative Design of Critical Software Tools
Engineers use software tools to analyze designs for critical systems. Because important decisions are based on tool results, tools must provide valid modeling constructs; engineer...
David Coppit, Kevin J. Sullivan