10159 search results - page 60 / 2032 » System Design Validation Using Formal Models |
ASE
1998
13 years 7 months ago
1998
Software process improvement requires high level formalisms for describing project-specific, organizational and quality aspects. These formalisms must be convenient not only for ...
CODES
2000
IEEE
14 years 12 days ago
2000
IEEE
In current design practice synthesis tools play a key role, letting designers to concentrate on the specificationof the system being designed by carrying out repetitive tasks such...
DAC
1997
ACM
14 years 5 days ago
1997
ACM
Task scheduling forreactive real time systems is a di cult problem due to tight constraints that the schedule must satisfy. A static priority scheme is proposed here that can be f...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
FMCAD
2006
Springer
13 years 11 months ago
2006
Springer
In this paper we formally specify and verify an implementation of the IEEE802.11a standard physical layer based OFDM (Orthogonal Frequency Division Multiplexing) modem using the HO...