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» System Design Validation Using Formal Models
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RE
2001
Springer
14 years 8 days ago
Virtual Environment Modeling for Requirements Validation of High Consequence Systems
An essential type of “evidence”of the correctness of the requirements formalization process can be provided by human-based calculation. Human calculation can be significantly ...
Victor L. Winter, Dejan Desovski, Bojan Cukic
JCP
2008
116views more  JCP 2008»
13 years 7 months ago
Formal Verification and Visualization of Security Policies
Verified and validated security policies are essential components of high assurance computer systems. The design and implementation of security policies are fundamental processes i...
Luay A. Wahsheh, Daniel Conte de Leon, Jim Alves-F...
MEMOCODE
2007
IEEE
14 years 2 months ago
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalka...
TACAS
1998
Springer
81views Algorithms» more  TACAS 1998»
14 years 1 days ago
Formal Design and Analysis of a Gear Controller
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...
Magnus Lindahl, Paul Pettersson, Wang Yi
RSP
1998
IEEE
126views Control Systems» more  RSP 1998»
14 years 3 days ago
Testing Prototypes Validity to Enhance Code Reuse
The complexity of distributed systems is a problem when designers want to evaluate their safety and liveness. Often, they are built by integration of existing components with newl...
Didier Buchs, A. Diagne, Fabrice Kordon