10159 search results - page 85 / 2032 » System Design Validation Using Formal Models |
MATES
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. In this paper, an integrated approach for the modeling and the validation through simulation of multi-agent systems is proposed. The approach centers on the instantiation...
SAFECOMP
1998
Springer
13 years 11 months ago
1998
Springer
A method is described for the analysis and the verification of safety in software systems. The method offers a formal notation for describing the software structure, the means for ...
MEMOCODE
2003
IEEE
14 years 1 months ago
2003
IEEE
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
ECBS
2005
IEEE
14 years 1 months ago
2005
IEEE
The fulfillment of time requirements is one of the major acceptance criteria of safety-critical and real-time systems. They are dictated by the environment of these systems and a...
FDL
2007
IEEE
14 years 2 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...