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» System Exploration of SystemC Designs
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DATE
2005
IEEE
104views Hardware» more  DATE 2005»
14 years 2 months ago
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC
In this paper, we present a SoC design methodology joining the capabilities of UML and SystemC to operate at systemlevel. We present a UML 2.0 profile of the SystemC language expl...
Elvinia Riccobene, Patrizia Scandurra, Alberto Ros...
SBCCI
2003
ACM
136views VLSI» more  SBCCI 2003»
14 years 2 months ago
SystemC and the Future of Design Languages: Opportunities for Users and Research
There has been a lot of discussion, and a lot of confusion, about the various existing and new design languages recently. SystemC, SystemVerilog, Verilog2005, e, Vera, PSL/Sugar, ...
Grant Martin
FDL
2004
IEEE
14 years 21 days ago
Designing for dynamic partially reconfigurable FPGAs with SystemC and OSSS
This paper presents a new approach to design embedded systems based on dynamic partial reconfigurable FPGAs. The approach is intended to allow designing of systems with runtime re...
Andreas Schallenberg, Frank Oppenheimer, Wolfgang ...
ISCAS
2003
IEEE
135views Hardware» more  ISCAS 2003»
14 years 2 months ago
Formal verification of LTL formulas for SystemC designs
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...
Daniel Große, Rolf Drechsler
MEMOCODE
2010
IEEE
13 years 6 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler