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119
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ETS
2007
IEEE
105views Hardware» more  ETS 2007»
15 years 10 months ago
Communication-Centric SoC Debug Using Transactions
— The growth in System-on-Chip complexity puts pressure on system verification. Due to limitations in the pre-silicon verification process, errors in hardware and software slip...
Bart Vermeulen, Kees Goossens, Remco van Steeden, ...
97
Voted
DAC
1994
ACM
15 years 7 months ago
Experience with Image Compression Chip Design using Unified System Construction Tools
Pravil Gupta, Chih-Tung Chen, J. C. DeSouza-Batist...
133
Voted
USENIX
1990
15 years 4 months ago
Efficient User-Level File Cache Management on the Sun Vnode Interface
In developing a distributed file system, there are several good reasons for implementing the client file cache manager as a user-level process. These include ease of implementatio...
David C. Steere, James J. Kistler, Mahadev Satyana...
123
Voted
FDL
2008
IEEE
15 years 5 months ago
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
Jinhyun Cho, Soonwoo Choi, Soo Chae
136
Voted
PROCEDIA
2010
148views more  PROCEDIA 2010»
14 years 10 months ago
SysCellC: a data-flow programming model on multi-GPU
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...
Dominique Houzet, Sylvain Huet, Anis Rahman