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CORR
2006
Springer
116views Education» more  CORR 2006»
15 years 4 months ago
Memory Aware High-Level Synthesis for Embedded Systems
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
Gwenolé Corre, Eric Senn, Nathalie Julien, ...

Publication
453views
17 years 2 months ago
System Level Modeling of IEEE 802.16e Mobile WiMAX Networks: Key Issues
WiMAX has attracted a lot of attention recently in the telecommunication community including researchers, product developers and service providers. Numerous papers have been publis...
Raj Jain, Chakchai So-In, and Abdel-Karim Al Tamim...
ISQED
2007
IEEE
104views Hardware» more  ISQED 2007»
15 years 10 months ago
System Level Estimation of Interconnect Length in the Presence of IP Blocks
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
15 years 7 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
CEC
2007
IEEE
15 years 10 months ago
Enabling generative behavior within an interactive evolutionary design system using a component-based representation
- The paper describes further research relating to an Interactive Evolutionary Design system (IEDS) with emphasis upon extending it to support free-form design. A generative feedba...
Azahar T. Machwe, Ian C. Parmee