Sciweavers

12333 search results - page 28 / 2467
» System Level Modelling for Hardware Software Systems
Sort
View
CASES
2006
ACM
14 years 3 months ago
Automatic performance model construction for the fast software exploration of new hardware designs
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
John Cavazos, Christophe Dubach, Felix V. Agakov, ...
ASPDAC
2004
ACM
106views Hardware» more  ASPDAC 2004»
14 years 2 months ago
A novel memory size model for variable-mapping in system level design
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...
Lukai Cai, Haobo Yu, Daniel Gajski
FPL
2004
Springer
83views Hardware» more  FPL 2004»
14 years 2 months ago
System-Level Modeling of Dynamically Reconfigurable Co-processors
Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the perfor...
Yang Qu, Kari Tiensyrjä, Kostas Masselos
ECBS
2010
IEEE
200views Hardware» more  ECBS 2010»
13 years 7 months ago
Improving Testing of Enterprise Systems by Model-Based Testing on Graphical User Interfaces
Software development and testing of Enterprise Resource Planning (ERP) systems demands dedicated methods to tackle its special features. As manual testing is not able to systematic...
Sebastian Wieczorek, Alin Stefanescu
COMPSAC
2007
IEEE
14 years 1 months ago
Unified Property Specification for Hardware/Software Co-Verification
Hardware/software co-verification is becoming an indispensable tool for building highly trustworthy embedded systems. A stumbling block to effective co-verification using model ch...
Fei Xie, Huaiyu Liu