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ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 3 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
EUROMICRO
2000
IEEE
13 years 11 months ago
A Simulink(c)-Based Approach to System Level Design and Architecture Selection
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
Luciano Lavagno, Begoña Pino, Leonardo Mari...
ASPDAC
2008
ACM
107views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata
The information about the run-time behavior of software applications is crucial for enabling system level optimizations for embedded systems. This embedded Software Metadata inform...
Alexandros Bartzas, Miguel Peón Quiró...
CODES
1997
IEEE
13 years 11 months ago
System level memory optimization for hardware-software co-design
Koen Danckaert, Francky Catthoor, Hugo De Man
CODES
2005
IEEE
14 years 29 days ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...