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» System-Level Verification - A Comparison of Approaches
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MEMOCODE
2010
IEEE
13 years 5 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
APSCC
2006
IEEE
13 years 9 months ago
GHIDS: Defending Computational Grids against Misusing of Shared Resources
Detecting intrusions at host level is vital to protecting shared resources in grid, but traditional Host-based Intrusion Detecting System (HIDS) is not suitable for grid environme...
Guofu Feng, Xiaoshe Dong, Weizhe Liu, Ying Chu, Ju...
DAC
2005
ACM
14 years 8 months ago
Analysis of full-wave conductor system impedance over substrate using novel integration techniques
An efficient approach to full-wave impedance extraction is developed that accounts for substrate effects through the use of two-layer media Green's functions in a mixed-poten...
Xin Hu, Jung Hoon Lee, Jacob White, Luca Daniel
CASES
2010
ACM
13 years 5 months ago
Instruction selection by graph transformation
Common generated instruction selections are based on tree pattern matching, but modern and custom architectures feature instructions, which cannot be covered by trees. To overcome...
Sebastian Buchwald, Andreas Zwinkau
EURODAC
1994
IEEE
141views VHDL» more  EURODAC 1994»
13 years 11 months ago
Exact path sensitization in timing analysis
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
R. Peset Llopis