82 search results - page 8 / 17 » SystemC transaction level models and RTL verification |
FDL
2007
IEEE
14 years 1 months ago
2007
IEEE
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
FDL
2007
IEEE
13 years 11 months ago
2007
IEEE
Transaction-level modelling (TLM) is a poorlyterm, promising a level of abstraction like RTL (register transfer level), where the key feature is a `transaction'. But unlike r...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...