Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
c Modular Abstractions for Linear Constraints David Monniaux VERIMAG June 27, 2008 se a method for automatically generating abstract transformers for static by abstract interpreta...
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
This poster presents a design language and a tool suite covering the development life-cycle of a Sense/Compute/Control (SCC) application. This language makes it possible to define...
This paper tackles the problem of providing correct information about program variable values in a software-pipelined loop through a non-transparent debugging approach. Since mode...