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141
Voted
CODES
2008
IEEE
15 years 10 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
147
Voted
CODES
2008
IEEE
15 years 10 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
157
Voted
DSRT
2008
IEEE
15 years 10 months ago
Interfacing and Coordination for a DEVS Simulation Protocol Standard
The DEVS formalism has been adopted and developed independently by many research teams, which led to various DEVS implementation versions. Consequently, different DEVS implementat...
Khaldoon Al-Zoubi, Gabriel A. Wainer
139
Voted
SASO
2008
IEEE
15 years 10 months ago
nuBOINC: BOINC Extensions for Community Cycle Sharing
Currently, cycle sharing over the Internet is a one-way deal. Computer owners only have one role in the process: to donate their computers’ idle time. This is due to the fact th...
João Nuno Silva, Luís Veiga, Paulo F...
148
Voted
CLUSTER
2007
IEEE
15 years 10 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...
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