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FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 11 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
ICDCS
1997
IEEE
13 years 11 months ago
Evaluating CORBA Latency and Scalability Over High-Speed ATM Networks
Conventional implementations of CORBA communication middleware incur significant overhead when used for performance-sensitive applications over high-speed networks. As gigabit ne...
Douglas C. Schmidt, Aniruddha S. Gokhale
SPAA
1996
ACM
13 years 11 months ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
IPCAI
2010
13 years 11 months ago
Evaluation of a 4D Cone-Beam CT Reconstruction Approach Using an Anthropomorphic Phantom
Abstract. We have previously developed image-guided navigation systems for thoracic abdominal interventions utilizing a three dimensional (3D) Cone-Beam CT (CBCT) image acquired at...
Ziv Yaniv, Jan Boese, Marily Sarmiento, Kevin Clea...
ELPUB
2007
ACM
13 years 11 months ago
Beyond Publication - A Passage Through Project StORe
The principal aim of Project StORe is to provide middleware that will enable bi-directional links between source repositories of research data and the output repositories containi...
Graham Pryor