78 search results - page 11 / 16 » Target Based Accepting Networks of Evolutionary Processors |
JSA
2010
13 years 1 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
FPL
2005
Springer
14 years 7 days ago
2005
Springer
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
NDSS
2009
IEEE
14 years 1 months ago
2009
IEEE
Coordinated attacks, where the tasks involved in an attack are distributed amongst multiple sources, can be used by an adversary to obfuscate his incursion. In this paper we prese...
IPPS
2006
IEEE
14 years 22 days ago
2006
IEEE
This paper describes a parallel implementation of our recently developed algorithm for phylogenetic analysis on the IBM BlueGene/L cluster [15]. This algorithm constructs evolutio...