54 search results - page 9 / 11 » Teaching Hardware Description and Verification |
ICALP
2009
Springer
14 years 7 months ago
2009
Springer
We present an AC1 (logDCFL) algorithm for checking LTL formulas over finite paths, thus establishing that the problem can be efficiently parallelized. Our construction provides a f...
ISCAS
2003
IEEE
14 years 21 days ago
2003
IEEE
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...
FMCAD
2008
Springer
13 years 9 months ago
2008
Springer
The extensional theory of arrays is one of the most important ones for applications of SAT Modulo Theories (SMT) to hardware and software verification. Here we present a new T-solv...
MEMOCODE
2010
IEEE
13 years 5 months ago
2010
IEEE
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
TCAD
2008
13 years 7 months ago
2008
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...