Today's fast-growing data-intensive network services place heavy demands on the backend servers that support them. This paper introduces ISTORE, an intelligent server archite...
Aaron B. Brown, David L. Oppenheimer, Kimberly Kee...
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
We present a methodology, an environment and supporting tools to map an application on a wireless sensor network (WSN). While the method is quite general, we use extensively an exa...
Alvise Bonivento, Luca P. Carloni, Alberto L. Sang...
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
: At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map rapidly and efficiently signal processing applications written ...
Steven Derrien, Alexandru Turjan, Claudiu Zissules...