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ATVA
2006
Springer
131views Hardware» more  ATVA 2006»
15 years 8 months ago
Timed Unfoldings for Networks of Timed Automata
Whereas partial order methods have proved their efficiency for the analysis of discrete-event systems, their application to timed systems remains a challenging research topic. Here...
Patricia Bouyer, Serge Haddad, Pierre-Alain Reynie...
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 8 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 8 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
ATVA
2008
Springer
131views Hardware» more  ATVA 2008»
15 years 6 months ago
Computation Tree Regular Logic for Genetic Regulatory Networks
Model checking has proven to be a useful analysis technique not only for concurrent systems, but also for the genetic regulatory networks (Grns) that govern the functioning of livi...
Radu Mateescu, Pedro T. Monteiro, Estelle Dumas, H...
ACSD
2006
IEEE
102views Hardware» more  ACSD 2006»
15 years 6 months ago
Models of Computation for Networks on Chip
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
Axel Jantsch