1355 search results - page 7 / 271 » Techniques for Formal Verification of Digital Systems: A Sys... |
ISARCS
2010
13 years 9 months ago
2010
Methods of formal description and verification represent a viable way for achieving fundamentally bug-free software. However, in reality only a small subset of the existing operati...
TCAD
2008
13 years 7 months ago
2008
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
FMCAD
2004
Springer
13 years 11 months ago
2004
Springer
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...
FM
2003
Springer
14 years 28 days ago
2003
Springer
We present the formal framework for a novel approach for specifying and automatically implementing systems such as digital circuits and network protocols. The goal is to reduce the...
TAP
2008
Springer
13 years 7 months ago
2008
Springer
Formal methods can only gain widespread use in industrial software development if they are integrated into software development techniques, tools, and languages used in practice. A...