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» Techniques for Region-Based Register Allocation
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ISSS
1996
IEEE
103views Hardware» more  ISSS 1996»
13 years 11 months ago
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
Guido Araujo, Ashok Sudarsanam, Sharad Malik
CF
2009
ACM
14 years 2 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
APPROX
2009
Springer
107views Algorithms» more  APPROX 2009»
14 years 2 months ago
Approximations for Aligned Coloring and Spillage Minimization in Interval and Chordal Graphs
We consider the problem of aligned coloring of interval and chordal graphs. These problems have substantial applications to register allocation in compilers and have recently been ...
Douglas E. Carroll, Adam Meyerson, Brian Tagiku
TVLSI
2002
94views more  TVLSI 2002»
13 years 7 months ago
A network flow approach to memory bandwidth utilization in embedded DSP core processors
This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors,...
Catherine H. Gebotys
DAC
1997
ACM
13 years 11 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas