A network flow approach to memory bandwidth utilization in embedded DSP core processors

This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors, sixteen bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses, including constant data memory layout, while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size and utilize higher memory bandwidths without increasing cost.

• Type: Journal
• Year: 2002
• Where: TVLSI
• Authors: Catherine H. Gebotys
• Keywords: Dsp Processors, Memory Bandwidths, Network Flow, TVLSI 2002