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ICPP
2007
IEEE
15 years 9 months ago
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
As the number of computing and storage nodes keeps increasing, the interconnection network is becoming a key element of many computing and communication systems, where the overall...
Gaspar Mora, Pedro Javier García, Jose Flic...
MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
15 years 9 months ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...
181
Voted
EUROPAR
2009
Springer
15 years 7 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
140
Voted
ASSETS
2005
ACM
15 years 5 months ago
Automatic production of tactile graphics from scalable vector graphics
This paper presents a method to convert vector graphics into tactile representations for the blind. Generating tactile pictures from vector graphics is an important effort to bri...
Stephen E. Krufka, Kenneth E. Barner
154
Voted
MIDDLEWARE
2007
Springer
15 years 9 months ago
The case for aspect-oriented reflective middleware
The emergence of applications domains such as pervasive and autonomic computing has increased the need for customisation and dynamic adaptation of both distributed systems, and th...
Paul Grace, Eddy Truyen, Bert Lagaisse, Wouter Joo...