171 search results - page 33 / 35 » Technology mapping for domino logic |
FCCM
2005
IEEE
14 years 2 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
ASPDAC
2007
ACM
14 years 17 days ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
WWW
2008
ACM
14 years 9 months ago
2008
ACM
For extracting the characteristics a specific geographic entity, and notably a place, we propose to use dynamic Extreme Tagging Systems in combination with the classic approach of...
INTERACTION
2009
ACM
14 years 3 months ago
2009
ACM
DTD and its instance have been considered the standard for data representation and information exchange format on the current web. However, when coming to the next generation of w...
FPGA
2010
ACM
14 years 5 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...