203 search results - page 11 / 41 » Temporal Logic Verification Using Simulation |
RCC
2002
13 years 6 months ago
2002
In recent years Arvind's Group at MIT has shown the usefulness of term rewriting theory for the specification of processor architectures. In their approach processors specifi...
PTS
2008
13 years 8 months ago
2008
We present in this paper a framework, RMOR, for monitoring the execution of C programs against state machines, expressed in a textual (nongraphical) format in files separate from t...
FMCAD
2007
Springer
14 years 26 days ago
2007
Springer
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
DAC
2000
ACM
14 years 7 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...