203 search results - page 21 / 41 » Temporal Logic Verification Using Simulation |
166
Voted
DAC
2010
ACM
15 years 7 months ago
2010
ACM
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
127
Voted
VLSID
2008
IEEE
16 years 4 months ago
2008
IEEE
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
130
Voted
FUIN
2006
15 years 3 months ago
2006
Abstract. This paper describes an attempt to combine theorem proving and model-checking to formally verify real-time systems in a discrete time setting. The Timed Automata Modeling...
172
Voted
IFIP
2001
Springer
15 years 8 months ago
2001
Springer
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
130
Voted
TCAD
2002
15 years 3 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...