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» Temporal Logic Verification Using Simulation
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DATE
2006
IEEE
117views Hardware» more  DATE 2006»
14 years 23 days ago
Formal verification of systemc designs using a petri-net based representation
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
Daniel Karlsson, Petru Eles, Zebo Peng
DFG
2004
Springer
13 years 10 months ago
Modeling and Formal Verification of Production Automation Systems
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wo...
BIS
2010
159views Business» more  BIS 2010»
13 years 1 months ago
Comparing Intended and Real Usage in Web Portal: Temporal Logic and Data Mining
Nowadays the software systems, including web portals, are developed from a priori assumptions about how the system will be used. However, frequently these assumptions hold only par...
Jérémy Besson, Ieva Mitasiunaite, Au...
CAISE
2006
Springer
13 years 10 months ago
Modelling and Verifying of e-Commerce Systems
Static function hierarchies and models of the dynamic behaviour are typically used in e-commerce systems. Issues to be verifies are the completeness and correctness of the static f...
Andreas Speck
ENTCS
2006
142views more  ENTCS 2006»
13 years 6 months ago
Specialization of Interaction Protocols in a Temporal Action Logic
Temporal logics are well suited for the specification and verification of systems of communicating agents. In this paper we adopt a social approach to agent communication, where c...
Laura Giordano, Alberto Martelli, Camilla Schwind