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» Temporal Logic Verification of Lock-Freedom
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DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 8 days ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
SIGSOFT
2001
ACM
14 years 9 months ago
Combining UML and formal notations for modelling real-time systems
This article explores a dual approach to real-time software development. Models are written in UML, as this is expected to be relatively easy and economic. Then models are automat...
Luigi Lavazza, Gabriele Quaroni, Matteo Venturelli
ANSS
2006
IEEE
14 years 2 months ago
An Integrative Modelling Approach for Simulation and Analysis of Adaptive Agents
To simulate adaptive agents with abilities matching those of their real-world counterparts, a natural approach is to incorporate adaptation mechanisms such as classical conditioni...
Tibor Bosse, Catholijn M. Jonker, Jan Treur
DASFAA
2008
IEEE
137views Database» more  DASFAA 2008»
13 years 10 months ago
Efficient Mining of Recurrent Rules from a Sequence Database
We study a novel problem of mining significant recurrent rules from a sequence database. Recurrent rules have the form "whenever a series of precedent events occurs, eventuall...
David Lo, Siau-Cheng Khoo, Chao Liu 0001
TABLEAUX
1998
Springer
14 years 23 days ago
Model Checking: Historical Perspective and Example (Extended Abstract)
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
Edmund M. Clarke, Sergey Berezin