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» Temporal Logics and Model Checking for Fairly Correct System...
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APLAS
2007
ACM
14 years 1 months ago
The Semantics of "Semantic Patches" in Coccinelle: Program Transformation for the Working Programmer
We rationally reconstruct the core of the Coccinelle system, used for automating and documenting collateral evolutions in Linux device drivers. A denotational semantics of the syst...
Neil D. Jones, René Rydhof Hansen
FTRTFT
1998
Springer
14 years 1 months ago
Fair Synchronous Transition Systems and Their Liveness Proofs
We present a compositional semantics of synchronous systems that captures both safety and progress properties of such systems. The fair synchronous transitions systems (fsts) mode...
Amir Pnueli, Natarajan Shankar, Eli Singerman
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
FMSD
2006
119views more  FMSD 2006»
13 years 9 months ago
Feature interaction detection by pairwise analysis of LTL properties - A case study
A Promela specification and a set of temporal properties are developed for a basic call service with a number of features. The properties are expressed in the logic LTL. Interactio...
Muffy Calder, Alice Miller
MEMOCODE
2003
IEEE
14 years 2 months ago
Methods for exploiting SAT solvers in unbounded model checking
— Modern SAT solvers have proved highly successful in finding counterexamples to temporal properties of systems, using a method known as ”bounded model checking”. It is natu...
Kenneth L. McMillan