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ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
13 years 11 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun
CODES
2000
IEEE
14 years 1 days ago
Frequency interleaving as a codesign scheduling paradigm
Frequency interleaving is introduced as a means of conceptualizing and co-scheduling hardware and software behaviors so that software models with conceptually unbounded state and ...
JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
CLUSTER
2006
IEEE
13 years 11 months ago
Modeling Network Contention Effects on All-to-All Operations
One of the most important collective communication patterns used in scientific applications is the complete exchange, also called All-to-All. Although efficient complete exchange ...
Luiz Angelo Steffenel
AICT
2010
IEEE
240views Communications» more  AICT 2010»
12 years 11 months ago
Providing Security in 4G Systems: Unveiling the Challenges
— Several research groups are working on designing new security architectures for 4G networks such as Hokey and Y-Comm. Since designing an efficient security module requires a cl...
Mahdi Aiash, Glenford E. Mapp, Aboubaker Lasebae, ...
ERSA
2006
111views Hardware» more  ERSA 2006»
13 years 9 months ago
Promises and Pitfalls of Reconfigurable Supercomputing
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
Maya Gokhale, Christopher Rickett, Justin L. Tripp...