125 search results - page 6 / 25 » Tera-scale computing and interconnect challenges |
DAC
2009
ACM
14 years 7 months ago
2009
ACM
Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-chip communication bottleneck and improve performance over traditional two-dimensional...
EUROPAR
2009
Springer
14 years 1 months ago
2009
Springer
Optimal network performance is critical to efficient parallel scaling for communication-bound applications on large machines. With wormhole routing, no-load latencies do not increa...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
—1 In this paper we present a stochastic model order reduction technique for interconnect extraction in the presence of process variabilities, i.e. variation-aware extraction. It...
CADUI
2004
13 years 8 months ago
2004
: This paper describes a system that helps HCI practitioners and researchers manage and conduct experiments involving context-sensitive handheld applications, particularly related ...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...