1812 search results - page 16 / 363 » Test Early, Test Often |
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
ECBS
2011
IEEE
12 years 8 months ago
2011
IEEE
Abstract—With the availability of the off-the-shelf quadrocopter platforms, the implementation of autonomous unmanned aerial vehicle (UAV) has substantially been simplified. Suc...
ISSRE
2002
IEEE
14 years 1 months ago
2002
IEEE
Formal analysis of software is a powerful analysis tool, but can be too costly. Random search of formal models can reduce that cost, but is theoretically incomplete. However, rand...
ITC
1998
IEEE
14 years 20 days ago
1998
IEEE
This work proposes an approach to generate weighted random patterns which can maximally excite a circuit during its burn-in testing. The approach is based on a probability model a...
WCE
2007
13 years 9 months ago
2007
Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniq...