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» Test Generation and Fault Localization for Quantum Circuits
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VLSID
1998
IEEE
117views VLSI» more  VLSID 1998»
13 years 11 months ago
Partial Scan Selection Based on Dynamic Reachability and Observability Information
A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-d...
Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. R...
TVLSI
2008
133views more  TVLSI 2008»
13 years 7 months ago
Test Data Compression Using Selective Encoding of Scan Slices
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Zhanglei Wang, Krishnendu Chakrabarty
ITC
1996
IEEE
127views Hardware» more  ITC 1996»
13 years 11 months ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey
KBSE
2009
IEEE
14 years 2 months ago
Evaluating the Accuracy of Fault Localization Techniques
—We investigate claims and assumptions made in several recent papers about fault localization (FL) techniques. Most of these claims have to do with evaluating FL accuracy. Our in...
Shaimaa Ali, James H. Andrews, Tamilselvi Dhandapa...
ATS
2009
IEEE
111views Hardware» more  ATS 2009»
14 years 2 months ago
Dynamic Compaction in SAT-Based ATPG
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
Alejandro Czutro, Ilia Polian, Piet Engelke, Sudha...