1016 search results - page 120 / 204 » Test Generation for Designs with On-Chip Clock Generators |
JSAT
2010
13 years 3 months ago
2010
The design of a SAT-solver or the modification of an existing one is always followed by a phase of intensive testing of the solver on a benchmark of instances. This task can be ve...
LREC
2010
13 years 10 months ago
2010
This paper describes the first TTS evaluation campaign designed for Spanish. Seven research institutions took part in the evaluation campaign and developed a voice from a common s...
GLVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
FCCM
2011
IEEE
13 years 26 days ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
IIS
2000
13 years 10 months ago
2000
This paper reports briefly on the development of a new approach to evolutionary computation, called the Learnable Evolution Model or LEM. In contrast to conventional Darwinian-typ...