1016 search results - page 125 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ITC
1994
IEEE
14 years 1 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
CVPR
2003
IEEE
14 years 11 months ago
2003
IEEE
In this paper we explore object recognition in clutter. We test our object recognition techniques on Gimpy and EZGimpy, examples of visual CAPTCHAs. A CAPTCHA ("Completely Au...
SENSYS
2009
ACM
14 years 3 months ago
2009
ACM
Continuous and reliable operation of WSNs is notoriously difficult to guarantee due to hardware degradation and environmental changes. In this paper, we propose and demonstrate a ...
LCTRTS
2007
Springer
14 years 3 months ago
2007
Springer
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
AIEDAM
2007
13 years 9 months ago
2007
Because of the increasing complexity of products and the design process, as well as the popularity of computer-aided documentation tools, the number of electronic and textual desi...