1016 search results - page 12 / 204 » Test Generation for Designs with On-Chip Clock Generators |
DSD
2008
IEEE
14 years 2 months ago
2008
IEEE
We propose a method to efficiently design a “parity generator”, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designe...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
ITC
1992
IEEE
13 years 11 months ago
1992
IEEE
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...
FORTE
1998
13 years 9 months ago
1998
Abstract: We present a new algorithm for automatic test generation for multicast routing. Our algorithm processes a nite state machine (FSM) model of the protocol and uses a mix of...
TCAD
2002
13 years 7 months ago
2002
This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field (2 ), where each cell of the CA can store ...