Sciweavers

1016 search results - page 14 / 204
» Test Generation for Designs with On-Chip Clock Generators
Sort
View
WSNA
2003
ACM
14 years 26 days ago
Asymptotically optimal time synchronization in dense sensor networks
We consider the problem of synchronization of all clocks in a sensor network, in the regime of asymptotically high node densities. We formulate this problem as one in which all cl...
An-Swol Hu, Sergio D. Servetto
ICCAD
2010
IEEE
141views Hardware» more  ICCAD 2010»
13 years 5 months ago
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...
ITC
1993
IEEE
110views Hardware» more  ITC 1993»
13 years 11 months ago
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A...
ACMSE
2006
ACM
14 years 1 months ago
Using genetic algorithms to generate test plans for functionality testing
Like in other fields, computer products (applications, hardware, etc.), before being marketed, require some level of testing to verify whether they meet their design and function...
Francisca Emanuelle Vieira, Francisco Martins, Raf...